Encoding:

Format:

SUBUH[_R].QB 

SUBUH.QB    rd, rs, rt

SUBUH_R.QB  rd, rs, rt

Purpose:

Subtract Unsigned Bytes And Right Shift to Halve Results

Element-wise subtraction of two vectors of unsigned bytes, with a one-bit right shift to halve resul ts and optional rounding.

Description:

rd = sign_extend(round((rs31..24 - rt31..24)>>1) || round((rs23..16 - rt23..16)>>1) || round((rs15..8 - rt15..8)>>1) || round((rs7..0 - rt7..0)>>1))

The four right-mostunsigned byte values in register rt are subtracted from the corresponding unsigned byte values in register rs. Each unsigned result is then halved by shifting right by one bit position. The byte results are then written to the corresponding elements of destination register rd.

In the rounding variant of the instruction, a value of 1 is added to the result of each subtraction at the discarded bit position before the right shift.

The sign of the left-most byte result is extended into the 32 most-significant bits of the destination register.

The results of this instruction never overflow; no bits of the ouflag field in the DSPControl register are written.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SUBUH.QB:
   tempD7..0 = ( ( 0 || GPR[rs]31..24 ) - ( 0 || GPR[rt]31..24 )) >> 1
   tempC7..0 = ( ( 0 || GPR[rs]23..16 ) - ( 0 || GPR[rt]23..16 )) >> 1
   tempB7..0 = ( ( 0 || GPR[rs]15..8 ) - ( 0 || GPR[rt]15..8 )) >> 1
   tempA7..0 = ( ( 0 || GPR[rs]7..0 ) - ( 0 || GPR[rt]7..0 )) >> 1
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
SUBUH_R.QB:
   tempD7..0 = ( ( 0 || GPR[rs]31..24 ) - ( 0 || GPR[rt]31..24 ) + 1) >> 1
   tempC7..0 = ( ( 0 || GPR[rs]23..16 ) - ( 0 || GPR[rt]23..16 ) + 1) >> 1
   tempB7..0 = ( ( 0 || GPR[rs]15..8 ) - ( 0 || GPR[rt]15..8 ) + 1) >> 1
   tempA7..0 = ( ( 0 || GPR[rs]7..0 ) - ( 0 || GPR[rt]7..0 ) + 1) >> 1
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0

Exceptions:

Reserved Instruction, DSP Disabled